[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #35 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #33)
> (In reply to Jacob Lifshay from comment #32)
> 
> > If I were to pick a replacement name for POWER9 when you meant the Power
> > ISA, I'd probably just pick Power,
> 
> unfortunately, Power is a general english word.
> 
> > since are docs clearly state (or should
> > state) that we're compatible with Power ISA v3.0B (or v3.1B). We can assume
> > someone reading our code knows that since that's what we advertise (or at
> > least knows that they should figure out which version we implement).
> 
> heck, *i* can't :)  or i do but not how to refer to it.  "Power" is far too
> general.  i have conversations with ordinary people, i have to refer them to
> PowerPC and mention "G4 Mac" and their eyes un-glaze at that point :)

Use PowerISA? PowerPC seems overly specific to old versions of the ISA, though
that *is* what gcc, llvm, and rust uses (powerpc64). Maybe PPC64?

> somewhere in the middle of the hardware pipeline you'll need to generate
> that overflow condition and pass it through.  whether that's a special
> flag or whether you actually use the xer_ov/32 data structure is up to you,
> but it has to come _out_ as xer_ov/32 and xer_ca/32 when it goes into
> ALUOutputStage.
> 
>         self.dive_abs_overflow_32 = Signal(reset_less=True)
>         self.dive_abs_overflow_64 = Signal(reset_less=True)

see DivOutputStage for the rest of the overflow calculation:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/div/output_stage.py;h=88a9ec1eec4bbc4ebb3fece42bbe235a13ae57ff;hb=HEAD#l65

> 
> ahhh excellent, you're on the ball :)

yup, only missing unit tests and formal proofs.

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