[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory object needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=382

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |yimmanuel3 at gatech.edu

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
found another
https://git.m-labs.hk/M-Labs/HeavyX

heavycomps/heavycomps/wishbone.py contains an SRAM.

-- 
You are receiving this mail because:
You are on the CC list for the bug.