[Libre-soc-bugs] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #14)
> (In reply to Luke Kenneth Casson Leighton from comment #12)
> > If an attempt is made to perform any of the divisions
> > <anything> % 0 0x8000_0000_0000_0000 % -1
> 
> Those are just the conditions where the corresponding div* instruction would
> overflow.

ok.

> > 
> > that's likely going to have to be special-cased as well, or at least tested
> > and we work out what is supposed to be put into RT.
> 
> already done:
> https://salsa.debian.org/Kazan-team/power-instruction-analyzer/-/blob/
> 13dae100c6bc5685059195010ceb46ae68b9f306/src/instr_models.rs#L195

brilliant.

> > interestingly these
> > do *not* result in overflow flags being set.
> 
> To clarify my previous statement, the OV, OV32, and SO flags are only set
> when the div*o variant of the instructions is selected but that doesn't
> exist for the mod* instructions, that's because div* is XO-form and mod* is
> X-form. I'm assuming ALUOutputStage will handle that wrinkle, though didn't
> yet check.

yes it does.  microwatt's source (now in the CSV files) sets on a per-op basis
whether followup OV/OV32/SO shall be actioned.  the Simulator ISACaller uses
the *exact* same PowerDecoder2 to determine this exact same information.

-- 
You are receiving this mail because:
You are on the CC list for the bug.