[Libre-soc-bugs] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #61 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #60)
> (In reply to Cesar Strauss from comment #59)
> > Did you consider implementing the ALU CompUnit as a pipeline?
> 
> you mean, MultiCompUnit itself?  if so: this would violate the
> mission-critical
> protocol, the purpose for which MultiCompUnit exists.

I understand that MultiCompUnit is sequential by contract, and that allowing
multiple operations in flight is a violation of that protocol.

That was not my idea when I conceived using the pipeline API in the design of
MultiCompUnit.

The idea was to use the pipeline API to enforce sequential operation
(eliminating all complex FSMs), and at the same time enforcing the ready/valid
and rel/go protocols for free.

Is started when I suspected that the rel/go protocol of the src and dest ports
maybe were compatible with the valid/ready protocol of the ALU.

I was then that I conceived of the src and dest ports being joined to the ALU
using the pipeline API.

The only thing, is making sure that only one operation is in flight in the
pipeline at a any time. A simple FSM would take care of that, I think.

But then, I would be crippling the power of the pipeline concept, which does
seems like a waste.

Oh well, at least I conceived an example of a parallel, dynamically
reconfigurable pipeline, with new elements like cross-switches and
barriers/combinators, that are maybe useful in other contexts.

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