[Libre-soc-bugs] [Bug 558] gcc SV intrinsics concept

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=558

--- Comment #32 from Jacob Lifshay <programmerjake at gmail.com> ---
the way I was imagining it would work is that VL is a register that can be
register allocated like normal, copy from VL would be mfspr, copy to VL would
be setvl with MAXVL=64, and there would be a separate setvl compiler op that
ttanslates to setvl with MAXVL set to the length of the vector types in the
vectorized code (or just setvli to set VL to MAXVL).

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