[Libre-soc-bugs] [Bug 550] binutils support needed for svp64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=550

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #6)
> thanks for the crash course.  as I said in the call, it was very useful.
> it's all beginning to make sense.

ah good.  it's kinda surprising that nobody has thought of this before.

> > we can "get away with this" by specifying the mode-type as part of the
> svp64 encoding... for now.
> 
> I was going to ask about that.  it seems that there's nothing in the svp64
> prefix instruction itself that tells how to decode its fields, you have to
> look at the actual insn that follows to know.

correct.  bit (haha) annoying however with bits so precious it's how it goes.
the alternative is that we request a Major Opcode then use the 2 extra bits,
one for 1/2 Predication, the other for 2/3 EXTRA (although to be honest, 2 more
bits means 4 more modes/features...)

the sv_analysis.py program is generating tables already
https://libre-soc.org/openpower/opcode_regs_deduped/

the idea is to create CSV files which give those 2 missing bits.  it is not
outside the realm of possibility to autogenerate a header file for inclusion in
binutils.

> Once we get to a stage in which we'll want to specify svp64 fields
> separately, rather than combined into a 24-bit immediate, an explicit
> specification of mode may help the assembler, to some extent, 

autogenerated.  otherwise it's too much work (200 insns) and you get
transcription errors.  dunno bout you but i don't want to have to check that.

> but the
> disassembler (and the assembler, if it's to detect inconsistencies) will
> have to look at prefix+insn as a single thing to be able to do its job.

indeed.  and PowerDecoder2 as well.  this is how it goes.

i'm not happy about it because normally RISC is not supposed to have lots of
gates in the decoder.

if we were doing our own ISA from scratch these two bits, saying whether 1P/2P
was set and whether EXTRA2/3 was set would definitely be part of the opcode.

-- 
You are receiving this mail because:
You are on the CC list for the bug.