[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #14 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)
> okaay, here we go.  "make lvx" in soclayout experiments12
> 
> 
> 1. Executing RTLIL frontend.
> Input filename: memory.il
> 
> 2. Executing HIERARCHY pass (managing design hierarchy).
> 
> 2.1. Analyzing design hierarchy..
> Top module:  \memory
> ERROR: Module `\SPBlock_512W64B8W' referenced in module `\memory' in cell
> `\U$$0' is not part of the design.
> mk/synthesis-yosys.mk:50: recipe for target 'memory.blif' failed
> make: *** [memory.blif] Error 1
> 
> 
> this is what i was expecting: there is no Cell Library for yosys to
> "understand" the block named SPBlock_512W6B48W.  how is that solved?

I can of think of some solutions:
* Custom yosys code that defines the external cell
* An empty verilog module for the block, yosys scripting then has to mark the
block as external so it is not removed
* A liberty file for the SRAM block (like there is for the cells). This would
contain the pins but no timing.

I think it is Jean-Paul who has to look at which solution is the best for his
Coriolis flow.

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