[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #11 from Staf Verhaegen <staf at fibraservi.eu> ---
Currently I SPBlock_512W64B8W as name of the 4K SRAM block. This should be the
nmigen code to include it:

    a = Signal(9)
    q = Signal(64)
    d = Signal(64)
    we = Signal(8)
    sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we)
    m.submodules += sram

How to do the conversion to litex I don't know.

Using this should allow to generate Verilog netlist that instantiates the SRAM
blocks.

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