[Libre-soc-bugs] [Bug 230] Video opcode development and discussion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=230

--- Comment #44 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #43)

> We will need variable shift-left/bitwise-shift-right/arithmetic-shift-right
> and maybe rotates too for GPU applications, so since we will already have
> them, you might as well use them.

indeed: however there are two different places.

1)  srcelwidth == destelwidth.

the normal place is in fixed-width Vector inputs.  64 bit RA/RB in or 2x32-bit
SIMD RA/RB in, 64 bit out or 2x32-bit SIMD out.

applying standard variable shift-right/etc. at that point - when srcwidth ==
destwidth - i have no problem with putting down large blocks, QTY 4 or 8 of
these, when the input data RA % 4 == RB % 4 == RT %4.

2)  srcelwidth != destelwidth

this is where the Monster FSM with the 256+ bit Shift Register comes into its
own.  here it's *not* ok to drop a massive set of gates down without some
Serious Thought going into it.

the idea here is to basically have some sort of subset of shift/mask that can
cope with and adapt to varying pixel in/out and audio in/out patterns, but
*without* having to design a full suite of operations that basically duplicates
the entire OpenPOWER rotate ISA.


but, that aside: yes if (2) doesn't work out then the fallback option would be
to at least get the data widened/expanded, use parallel vector shift/mask (same
src/dest width)

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