[Libre-soc-bugs] [Bug 230] Video opcode development and discussion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=230

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to cand from comment #26)
> Added under the msum point.

star.

ok so *sigh* there's a couple of options here:

1) we actually add a 4-wide (actual SIMD) instruction.  yuk.
2) we add opcodes "horizontal-add", "horizontal-mul" which work *only* on
   vec2, vec3 and vec4.

so when you ask, "But can the SV loop increment the src reg # by 4? Hmm."
the answer is: yes... as long as it's a vec2, vec3 or vec4 as the src
regs.

the dest would remain non-vec2/3/4 which is what makes the operation extremely
unusual.

the other one involves 32-bit src and 128-bit dest so i'll need to think about
it.  

    rd = (rs >> 0 * 8) & (2^8 - 1)
    rd+1 = (rs >> 1 * 8) & (2^8 - 1)
    rd+2 = (rs >> 2 * 8) & (2^8 - 1)
    rd+3 = (rs >> 3 * 8) & (2^8 - 1)

this particular pattern, it's actually using the SUBVL as the immediate in the
shift.

-- 
You are receiving this mail because:
You are on the CC list for the bug.