[Libre-soc-bugs] [Bug 545] New: Some errors and failures when running tests, with recent nMigen

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=545

            Bug ID: 545
           Summary: Some errors and failures when running tests, with
                    recent nMigen
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: cestrauss at gmail.com
          Reporter: cestrauss at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

Lately, as I test nMigen CxxSim, I began to systematically run a greater number
of tests than I was used to, as well as keeping nMigen itself updated.

Here is a summary of the results.

Simulator: PySim

Commit IDs:

1) Libre-SOC:
commit 9380181f4c19e845730c8fbbecf18fcbfc9b6f06 (HEAD -> master, origin/master,
origin/HEAD)
Author: Cesar Strauss <cestrauss at gmail.com>
Date:   Mon Dec 7 18:44:40 2020 -0300

    Display the instruction type as a vector on cxxsim

2) nmutil:
commit 32a50f48658d5250305a6a4ac8e738c93a44038f (HEAD -> master, origin/master,
origin/HEAD)
Author: Cesar Strauss <cestrauss at gmail.com>
Date:   Sun Dec 6 08:47:37 2020 -0300

    Implement the "submodule" attribute

3) pia:
commit 5f7d8c0e32c6aeba8533553b77e6261018b84c06 (HEAD -> master, tag: v0.2.0,
origin/master, origin/HEAD)
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Wed Oct 28 16:56:57 2020 -0700

    add crate descriptions

4) nmigen-soc
commit 692017c7eaf21ff37302790c4422db6bd08667be (HEAD -> master, origin/master,
origin/HEAD)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Thu Oct 1 18:15:54 2020 +0100

    must not delay ack to wb request in SRAM

5) nMigen:
commit 2f8231d961cda20756226a310fdf20279046b801 (HEAD -> cxxsim, origin/cxxsim)
Author: whitequark <whitequark at whitequark.org>
Date:   Mon Dec 7 10:54:06 2020 +0000

    sim.cxxsim: preserve reset value of toplevel inputs.

Test results:

1) Tests with syntax errors:
src/soc/fu/alu/formal/proof_input_stage.py
src/soc/fu/alu/formal/proof_output_stage.py
src/soc/fu/branch/formal/proof_input_stage.py
src/soc/fu/branch/formal/proof_main_stage.py
src/soc/fu/cr/formal/proof_main_stage.py
src/soc/fu/div/formal/proof_main_stage.py
src/soc/fu/logical/formal/proof_input_stage.py
src/soc/fu/logical/formal/proof_main_stage.py
src/soc/fu/mul/formal/proof_main_stage.py
src/soc/fu/shift_rot/formal/proof_main_stage.py
src/soc/regfile/formal/proof_regfile_binary.py
src/soc/decoder/formal/proof_decoder2.py 
src/soc/decoder/test/test_decoder_gas.py
src/soc/experiment/compldst_multi.py 
src/soc/experiment/cscore.py 
src/soc/experiment/imem.py 
src/soc/experiment/lsmem.py 
src/soc/experiment/score6600.py 
src/soc/experiment/score6600_multi.py 
src/soc/experiment/test/async_sim.py

2) Tests that fails assertions:
src/soc/simple/test/test_issuer.py
src/soc/decoder/test/test_power_decoder.py
src/soc/decoder/test/test_decoder_gas.py
src/soc/fu/mul/test/test_pipe_caller.py 
src/soc/fu/trap/test/test_pipe_caller.py
src/soc/fu/compunits/test/test_trap_compunit.py 
src/soc/fu/logical/test/test_pipe_caller.py
src/soc/fu/compunits/formal/proof_fu.py
src/soc/fu/alu/formal/proof_main_stage.py
src/soc/fu/spr/formal/proof_main_stage.py
src/soc/fu/trap/formal/proof_main_stage.py
src/soc/regfile/formal/proof_regfile.py
src/soc/regfile/formal/proof_regfile_array.py
src/soc/decoder/formal/proof_decoder.py 
src/soc/experiment/icache.py 

3) Tests that hangs (enters infinite loops):
src/soc/experiment/l0_cache.py 
src/soc/fu/compunits/test/test_logical_compunit.py 

4) Tests that run without any problems:
src/soc/fu/alu/test/test_pipe_caller.py 
src/soc/fu/branch/test/test_pipe_caller.py 
src/soc/fu/cr/test/test_pipe_caller.py 
src/soc/fu/div/test/test_pipe_caller.py 
src/soc/fu/mmu/test/test_pipe_caller.py 
src/soc/fu/shift_rot/test/test_pipe_caller.py 
src/soc/fu/spr/test/test_pipe_caller.py 
src/soc/fu/compunits/test/test_alu_compunit.py 
src/soc/fu/compunits/test/test_branch_compunit.py 
src/soc/fu/compunits/test/test_cr_compunit.py 
src/soc/fu/compunits/test/test_div_compunit.py 
src/soc/fu/compunits/test/test_ldst_compunit.py 
src/soc/fu/compunits/test/test_shiftrot_compunit.py 
src/soc/fu/compunits/test/test_spr_compunit.py 
src/soc/experiment/alu_fsm.py 
src/soc/experiment/alu_hier.py 
src/soc/experiment/dcache.py 
src/soc/experiment/mmu.py 
src/soc/experiment/test/test_compalu_multi.py 
src/soc/experiment/test/test_l0_cache_buffer2.py 
src/soc/experiment/test/test_mmu_dcache.py 
src/soc/experiment/test/test_mmu_dcache_pi.py 
src/soc/fu/logical/formal/proof_bpermd.py
src/soc/experiment/formal/proof_alu_fsm.py 
src/soc/experiment/formal/proof_datamerger.py

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