[Libre-soc-bugs] [Bug 230] Video opcode development and discussion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=230

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #17)
> (In reply to Luke Kenneth Casson Leighton from comment #16)
> > SIMD ISAs have the "advantage" of being able to hard-code the mapreduce tree
> > (or parallel accumulator algorithm) because the SIMD size is fixed and known.
> 
> That can be done in SV as well, since MAXVL is fixed and known, 

in RVV, yes, MAXVL is hardcoded to the number of microarchitectural lanes.

in SV, MAXVL sets the maximum length of the allocation of the regfile that may
be used for the vector operation *and may be set to anywhere between 1 and 64*
at runtime, at any time.  MAXVL=1 says "all ops are flatlined to scalar".

consequently, no, MAXVL may not be assumed to be hard-coded to 4, 8, or 16, as
would be the case for RVV or any SIMD microarchitecture.

thus we cannot hardcode a series of mapreduce crossbars or allocate some
hardcoded lane paths (called "wires"), like a SIMD microarchitecture would.

instead we need a micro-coded approach, and that's the CISC path which i would
prefer we deprioritise until we get more information.

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