[Libre-soc-bugs] [Bug 230] Video opcode development and discussion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=230

--- Comment #14 from cand at gmx.com ---
Consider how long it took for you to think it through and how long the text
describing it is. Now consider it is a one-line operation in SIMD ISAs. This
means nobody will bother coding it in SV, handicapping it.

Now, I'm not saying we have to have it fully in hw. A mid-step that just does
it for 4 or 8 elements, in one clock, would be close enough. That would
hopefully also side-step the slowness in non-4-reg-stalls. That's still a loop,
but just a simple one-level loop, no complexity.

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