[Libre-soc-bugs] [Bug 48] Complete IEEE754 floating point pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=48
Bug 48 depends on bug 76, which changed state.

Bug 76 Summary: IEEE754 RISC-V "tininess" as well as rounding modes (odd/even) needed
https://bugs.libre-soc.org/show_bug.cgi?id=76

           What    |Removed                     |Added
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             Status|CONFIRMED                   |RESOLVED
         Resolution|---                         |INVALID

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