[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #66 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
looks great.  i would bullet these:

Next we will wire up the STLINKv2 and our FPGA in three separate stages.

* First a
...
...
* Finally.

also now i see it laid out, there is just too much wording in the tables.

the done column is extraneous space at the front.

the repetition "this is something something" is non-aligned.

i would suggest:

| action       | colour | pin | function | done |

then cut the extraneous verbose description, "Voltage ref is known as VREF".
why is that important to know as an instruction? it's not: it's information -
information that will distract someone who is trying to concentrate on doing
exactly the right task.

| connect F2F RED cable to pin # 5 | RED | 5 | TDO | |

no need to say "put female plug on pin" because it won't fit as a male pin :)
however if there is the slightest possibility of getting this wrong, leave it
in.

for the F2F cables however there is going to be no mistake.  the M2F ones on
the other hand...

no, those go on the STLINKv2 and no possibility of a mistake there either.

so in both cases the verbiage can go.

this may even get the instruction down to about 5-6 words, down from... 30?

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