[Libre-soc-bugs] [Bug 476] addme ALU pipeline bug

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=476

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 9486ce5933b5a20031166a1caffa0821b2af883f (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Thu Aug 27 21:18:12 2020 +0100

    https://bugs.libre-soc.org/show_bug.cgi?id=476
    XER SO not being "listened" to correctly when OE=0 and Rc=1 creating CR0

jacob this was another (arbitrary) test, coming from microwatt:

        lst = ["addme. 6, 16"]
        initial_regs = [0] * 32
        initial_regs[16] = 0x7ffffffff
        initial_sprs = {}
        xer = SelectableInt(0, 64)
        xer[XER_bits['CA']] = 1
        xer[XER_bits['SO']] = 1

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