[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #12 from Cole Poirier <colepoirier at gmail.com> ---
Hi Luke, I'm struggling with translating the generate statements and
generic/port maps, can you give me some feedback on whether the following is a
correct translation? Thank you :)

```dcache.vhdl
-- Generate TLB PLRUs
maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
begin
tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
    -- TLB PLRU interface
    signal tlb_plru_acc    : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
    signal tlb_plru_acc_en : std_ulogic;
    signal tlb_plru_out    : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
begin
tlb_plru : entity work.plru
    generic map (
        BITS => TLB_WAY_BITS
        )
    port map (
        clk => clk,
        rst => rst,
        acc => tlb_plru_acc,
        acc_en => tlb_plru_acc_en,
        lru => tlb_plru_out
        );

    process(all)
    begin
    -- PLRU interface
    if r1.tlb_hit_index = i then
        tlb_plru_acc_en <= r1.tlb_hit;
    else
        tlb_plru_acc_en <= '0';
    end if;
    tlb_plru_acc <=
std_ulogic_vector(to_unsigned(r1.tlb_hit_way,TLB_WAY_BITS));
    tlb_plru_victim(i) <= tlb_plru_out;
    end process;
end generate;
end generate;
```

```dcache.py
# Generate TLB PLRUs
def maybe_tlb_plrus(self, m, r1, tlb_plru_victim, acc, acc_en, lru):
    comb = m.d.comb
    sync = m.d.sync

    with m.If(TLB_NUM_WAYS > 1):
        for i in range(TLB_SET_SIZE):

            # TLB PLRU interface
            comb += tlb_plru.eq(object)
            comb += tlb_plru.input.tlb_plru_acc.eq(
                     Signal(TLB_WAY_BITS)
                    )    
            comb += tlb_plru.input.tlb_plru_acc_en.eq(Signal())
            comb += tlb_plru.input.tlb_plru_out.eq(
                     Signal(TLB_WAY_BITS)
                    )    
            comb += tlb_plru.input.tlb_plru_acc.eq(acc)
            comb += tlb_plru.input.tlb_plru_acc_en.eq(acc_en)
            comb += tlb_plru.input.tlb_plru_out.eq(lru)

            with m.If(r1.tlb_hit_index == i):
                comb += tlb_plru.input.tlb_plru_acc_en.eq(
                         r1.tlb_hit
                        )    

            with m.Else():
                comb += tlb_plru.tlb_plru_acc_en.eq(0)

            comb += tlb_plru.input.tlb_plru_acc.eq(
                     r1.tlb_hit_way
                    )    

            comb += tlb_plru_victim[i].eq(
                     tlb_plru.input.tlb_plru_out
                    )    
```

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