[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #64 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #62)
> hi jean-paul, we've still got a few routes not linked up.  there's actually
> very few, it's quite amazing.  can you take a look?  i'm just re-running
> "make layout" (we're dropping the hierarchichal effort for now), if i run
> into difficulties i'll let you know straight away

  I'm rebuilding it on my side as a I wrote this... I will look for
  the fine tuning.

> btw just so you're aware: the current interfaces are *wishbone* interfaces,
> they're in no way intended for public external exposure via pins.  not
> unless we absolutely have to bring them out, that is.

  OK. Just to be clear, you mean that:

  1. They are extraneous and we can avoid putting them out.

  *or*

  2. Its the interface *for now* and it will change in the future to
     some normalized standard.

  If its the second case, to have a better approximation, we must keep
  the wishbone interface exported for now.


> we still have to fit a set of GPIO and i am currently sorting out Litex SIM
> to be able to at least have something even if it is utterly basic.

  OK.

  Some update from my side, I'm implementing a high fanout net synthesis
  algorithm which is roughly placement driven. As I'm experimenting
  various ways as I go, I do not commit because of very ephemeral
  stages.
    I'm also working with Staf on the TSMC 180nm portage to Coriolis.
    And, I'm (again) in vacation until Sunday 6, September, so the
  advance of the work will depend on the (bad) weather...
    By the way, the port 922 is filtered by the ISP of my current
  accommodation so I get them though my home box (after transforming
  the commits into patches). Writing this make me think I should
  have just made a ssh tunnel. Stupid of me.

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