[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #62 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hi jean-paul, we've still got a few routes not linked up.  there's actually
very few, it's quite amazing.  can you take a look?  i'm just re-running "make
layout" (we're dropping the hierarchichal effort for now), if i run into
difficulties i'll let you know straight away

btw just so you're aware: the current interfaces are *wishbone* interfaces,
they're in no way intended for public external exposure via pins.  not unless
we absolutely have to bring them out, that is.

we still have to fit a set of GPIO and i am currently sorting out Litex SIM to
be able to at least have something even if it is utterly basic.

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