[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #7 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Cole Poirier from comment #1)

> Luke, can you give me some guidance on this specifically relating to
> tranlading vhdl generate blocks, port maps, and generic maps into nmigen?
> (and a few other things that I've skipped due to lack of understanding but
> are marked in the file with comments that contain the keyword TODO).

I've finished my first translation pass of dcache.vhdl -> dcache.py.
As I stated in this commit I've left around 5% undone as they involved generate
and instance statements that I couldn't figure out how to translate and would
like some help and guidance on.

As I said in my earlier comment (quoted above), this also include inputs to
modules in the form of port and generic, maps.

Additionally I'm 100% sure I'm not setting up the classes/modules right, and
looking at mmu.py gives me a good idea of how to fix this. I just don't have
the energy left to do this today.

So, can you provide some corrections and help with the things I've asked for
(marked in the file with comments containing the keyword TODO), and leave for
me to make an attempt at tomorrow: the fixing of the arrangment of things I
created classes for into functions as they are in mmu.py?

Thanks, as always for your help and guidance :)

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