[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Mon Aug 24 01:51:07 BST 2020
https://bugs.libre-soc.org/show_bug.cgi?id=469
--- Comment #5 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> # subtype way_t is integer range 0 to NUM_WAYS-1;
>
>
> therefore wherever you *see* way_t, replace it with "NUM_WAYS".
>
> # hit_way : way_t;
>
> self.hit_way = Signal(WAY)
>
> no - this needs to be:
>
> self.hit_way = Signal(NUM_WAYS)
>
> likewise:
>
> # forward_row1 : row_t;
>
> self.forward_row1 = Signal(ROW)
>
> no - look at the definition of row_t:
>
> # subtype row_t is integer range 0 to BRAM_ROWS-1;
>
> therefore that needs to be:
>
> self.forward_row1 = Signal(BRAM_ROWS)
>
> etc. etc. exactly the same for INDEX, and probably CACHE_TAG as well.
So each subtype unless it is an array is simply an aliasing of the constant it
specifies directly or through one or more levels of subtyping indirection?
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