[Libre-soc-bugs] [Bug 393] Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
    NLnet milestone|---                         |NLNet.2019.10.Wishbone
 total budget (EUR)|0                           |300
  for completion of|                            |
       task and all|                            |
           subtasks|                            |
         Resolution|---                         |FIXED
             Status|CONFIRMED                   |RESOLVED
    parent task for|                            |383
  budget allocation|                            |

--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
TODO add error handling separately once dcache vhdl has been converted and
analysed.  this will tell us the full range of error messages required.

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