[Libre-soc-bugs] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=186

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
    parent task for|                            |383
  budget allocation|                            |
    NLnet milestone|NLnet.2019.02               |NLNet.2019.10.Wishbone
             Status|CONFIRMED                   |RESOLVED
             Blocks|                            |383
 total budget (EUR)|0                           |400
  for completion of|                            |
       task and all|                            |
           subtasks|                            |
         Resolution|---                         |FIXED

--- Comment #137 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
closing this, completed (POWER9, not doing RISCV).
EUR 200 michael, EUR 200 lkcl


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=383
[Bug 383] Complete first functional POWER9 Core
-- 
You are receiving this mail because:
You are on the CC list for the bug.