[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #46 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #45)
> (In reply to Cole Poirier from comment #44)
> > Am I allowed to use typing from the python standard library? With them I can
> > see how to translate dcache.vhdl... without them, I may need some guidance
> > here.
> 
> if they're in the .py file, i can't stand it.  the increased unnecessary
> verbiage is so frustrating and irrelevant i can't tolerate it.  not only
> do line lengths increase, they increase so far that function declarations
> which would otherwise easily fit on a single compact line have to end up
> as massive multi-line declarations, pretty much every time.
> 
> for no good reason.
> 
> if you absolutely must use them put them in a separate .pyi file and make
> sure to take responsibility for keeping them up-to-date (because i won't).

Ok types aren't actually going to help with my problem, what I need is a way to
express constraints on types, like the ranges of 'subtyped integers'.

For example from what I'm struggling to translate in dcache.vhdl:
```
# Number of ways
NUM_WAYS     =  4

subtype way_t is integer range 0 to NUM_WAYS-1;

subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);

type cache_tags_set_t is array(way_t) of cache_tag_t;
type cache_tags_array_t is array(index_t) of cache_tags_set_t;
```

How should I translate `type cache_tags_set_t is array(way_t) of cache_tag_t;`
into nmigen?

-- 
You are receiving this mail because:
You are on the CC list for the bug.