[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #33 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #32)
> (In reply to Luke Kenneth Casson Leighton from comment #31)
> > (In reply to Cole Poirier from comment #30)
> > > Several questions:
> > > 
> > > How do I specify a signal as a non-zero positive integer in nmigen?
> > 
> > unsigned is the default.
> 
> I'm aware. What I'm looking for is not n >= 0 but n > 0. Does this exist in
> nmigen?

with unsigned, "> 0" is equivalent to != 0.

> > > How should the assignment of a a value to a variable with the representation
> > > "(others => '0')" in vhdl,
> > 
> > drop it.
> 
> As in no variable assignment to tlb_data?

correct.

> Then why bother putting that line
> in the vhdl at all?

convenience for vhdl.  we are not doing vhdl.

> > > For example:
> > > ```
> > > tlb_data := (others => '0')
> > 
> > assign to zero.
> 
> This conflicts with your above statement. So assign tlb_data the value of 0?
> Why is it not then written as 'tlb_data := '0'

because it specifies all "other" bits not specified in the assignment between
the brackets.


> > usual way: writing a unit test (for example translating mmu_tb.vhdl)
> 
> Sounds good. What does the suffix _tb stand for by the way?

standard convention for files that include a "**T**est **B**ench"

> > AddrShifter needs to go, to be replaced by simply "shift" i.e. "<<".
> 
> Oh are we that lucky? I will delete that class now then.

it's an optimisation based on the assumption that yosys will not be able to
correctly produce optimal FPGA connections.

this will interfere with us doing an ASIC.

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