[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #31 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #30)
> Several questions:
> 
> How do I specify a signal as a non-zero positive integer in nmigen?

unsigned is the default.

> How should the assignment of a a value to a variable with the representation
> "(others => '0')" in vhdl,

drop it.

> For example:
> ```
> tlb_data := (others => '0')

assign to zero.

> ```
> 
> Is this translated correctly?

no.

> #       m := x"001f";

m = x"NNNN".  length of N (a hexadecimal digit) is 4.  4 time 4 is 16.

> Is this correct? If a statement X is wrapped in an or in vhdl, in nmigen it
> is 
> or'd with 0? i.e. 0 | X?
> 
> ```
> # nonzero := or(r.addr(61 downto 31) and
> #            not finalmask(30 downto 0));

i have already told you the answer to this one.  please read the comments from
the web interface, not via email, and read them *in full*, going back
repeatedly to make sure that you have understood them and not missed any.

> How do I start testing/getting this module to work?

usual way: writing a unit test (for example translating mmu_tb.vhdl)

> Should I just move on to
> translating icache.vhdl(~800 lines), d.cache.vhdl(~1600 lines), etc. because
> their incredibly tight integration with mmu.vhdl means that I should work
> concurrently on making them 'run' (work all of them together once they have
> all been translated 99%)?

no.  start on the unit test.  first, though, you've missed these RecordObjects:

 133         self.l_in  = Loadstore1ToMmuType()
 134         self.l_out = MmuToLoadstore1Type()
 135         self.d_out = MmuToDcacheType()
 136         self.d_in  = DcacheToMmuType()
 137         self.i_out = MmuToIcacheType()


> Also should AddrShifter, MaskGen, etc. classes be made submodules of MMU?

AddrShifter needs to go, to be replaced by simply "shift" i.e. "<<".

MaskGen i will review and work out if they are needed.

> Am I corectly initing things, and inheriting in nmigen in a way that
> properly corresponds to the vhdl, or even correct in terms of general python?

no idea, i will need to do a line-by-line compare.

> I know this is a lot of questions, but I'm unsure as to how I should
> progress from here, as I know I'm doing things wrong, but I don't know what
> specifically I have done wrong. My plan as of this moment is to start
> translating icache.vhdl into nmigen tomorrow.

add those RecordObjects first.

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