[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #27)
> (In reply to Luke Kenneth Casson Leighton from comment #26)
> > (In reply to Cole Poirier from comment #24)
> > 
> > > Ah, that's good. I'll take a proper look at the minerva code now, then.
> > 
> > not worth spending time on yet excrpt out of curiosity in passing.
> > 
> > eventually once all pieces dcache.vhdl icache.vhdl plru.vhdl mmu.vhdl are
> > done then it is worthwhile looking and converting to LoadStoreInterface and
> > FetchInterface.
> > 
> > until then which will be several days yet it is a distraction.
> 
> Oh... I took your previous comment to mean that I would *not* be converting
> dcache.vhdl nor icache.vhdl. Am I correct now in saying that all of "all
> pieces dcache.vhdl icache.vhdl plru.vhdl mmu.vhdl" must be converted to get
> mmu.py to work?

oh it will "work", it just will be useless unless tightly integrated into a d
and i cache (just like in microwatt)

without us having to have a seriously indepth technical understanding of
computer architectural design ... yes.

given that minerva's code does not include an mmu, examining minerva's cache
code is of little value in guiding us towards such an integrated
mmu-cache-memory subsystem (just like in microwatt)... *except* the one
abstract base class: LoadStoreInterface because that is what the vhdl code must
be modified to conform to (eventually)

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