[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #22 from Cole Poirier <colepoirier at gmail.com> ---
Is this going to require modifications/additions to LDSTUnit, L0Cache, L1Cache?

Just taking a look at microwatt's:

* common.vhdl
https://github.com/antonblanchard/microwatt/blob/master/common.vhdl
* loadstore1.vhdl
https://github.com/antonblanchard/microwatt/blob/master/loadstore1.vhdl
* icache.vhdl
https://github.com/antonblanchard/microwatt/blob/master/icache.vhdl
* dcache.vhdl
https://github.com/antonblanchard/microwatt/blob/master/dcache.vhdl

that's the impression I'm getting..

I know a lot of work has been done on LDSTUnit, and the cache was part of this.
To what extent are the I-cache and D-cache of the 180nm test ASIC complete?

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