[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
delete these exact lines.  do not do anything other than delete these lines
exactly as instructed.  do not try to do anything fancy such as "play guessing
games" such as occurred in the mul unit test.  just... delete lines 181 to 194.

the reason is that nmigen does not have the concept of "processes".  it is an
artificial construct.

therefore the creation of a totally separate module named MMU0 was unnecessary.

by deleting these lines, the lines *below* join the elaborate function *above*.
 this is what is desired.  do not try to do anything else or try to guess what
might be needed: just delete lines 181 to 194.

 181 # mmu_0: process(clk)
 182 class MMU0(Elaboratable):
 183     def __init__(self, clk):
 184         self.clk = clk
 185 
 186 # begin
 187     def elaborate(self, platform):
 188 
 189         m = Module()
 190 
 191         comb = m.d.comb
 192         sync = m.d.sync
 193 
 194         rst = ResetSignal()

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