[Libre-soc-bugs] [Bug 448] MUL pipeline unit tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=448

--- Comment #52 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #51)
> I updated (and pushed) mulli to what I thought would be the way to do it but
> I know I'm still doing it wrong... because the tests only have register 'ra'
> and it's always zero. 

you're looking at the output and finding discrepancies from expected behaviour.
 good.

> I don't know how to resolve this from looking at
> addi's use in the other unit tests.

 choice = random.choice(test_values)
 l = [f"mulli 1, 0, {choice}"]

this says, "multiply register 0 by the immediate X and put the result in
register 1, doesn't it?

 initial_regs = [0] * 32
 initial_regs[1] = random.randint(-1 << 15, (1 << 15) - 1)
 initial_regs[2] = random.randint(-1 << 15, (1 << 15) - 1)

here, register 1 and 2 have been set to a random value.

what is register 0 set to by the previous line?

so why are you surprised to find that exactly what you have asked to be done is
in fact being done?

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