[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #49 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
argh.

overnight i just realised something, jean-paul.

trying to put the oper_i on the side of each pipeline is completely pointless
*unless* decoder2 is in the middle and the pipelines are staggered like stairs:

#### ## ## ## ####
#### ## ## ## ####
#### ##    ## ####
####    dec   ####

so the *really* small pipelines are at the apex, the mediun sized ones either
side, abd the really big ones hard left or hard right (mul will be one of
those)

the staggered approach basically gives opwe er_i_* a chance to come in
horizontally into the corner...

... *WITHOUT* needing to do a right angle turn to get there.

if oper_i has to turn from vertical horizontal to get into the side of each
pipeline then the vertical channel between pipelines has to be as wide as if
you had made the pipeline itself that wide.

which is pointless.

a "staggered" step-up step-down "A Frame" layout with decode2 in the middle
will do it.

we need some sort of ASCII art diagram, really, don't we, which lays this out.

can you commit what you have so far and i will take a look and add a quick
diagram?

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