[Libre-soc-misc] How not to design instruction sets

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Dec 14 21:04:46 GMT 2020

On 12/14/20, Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Mon, Dec 14, 2020, 11:43 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>> On 12/14/20, Jacob Lifshay <programmerjake at gmail.com> wrote:
>> > I found this on the RISC-V mailing lists, looks interesting:
>> > https://player.vimeo.com/video/450406346
>> >
>> > it's a talk by one of the x86 AVX512 instruction set designers covering
>> the
>> > benefits and mistakes of AVX512.
>> oo fascinating.  nice find.
> One important thing they mentioned is that swizzles should not be combined
> with ALU ops. Combining them with load/stores is fine though.

yes i noted that.  expecting people to port SSE code except they just
chucked it out.

> I'm thinking that if we have the realignment network on the input of the
> ALUs anyway to handle packing the ALUs fuller when doing predicated ops
> (AVX512 doesn't do that), then swizzles might be fine to combine with ALU
> ops anyway.

see how it goes.  one thing to be careful of, fixed lane lengths vs
variable vectors, have to be extra careful.


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