[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|IN_PROGRESS                 |RESOLVED

--- Comment #18 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #17)
> ahh that's more like it. coment could do with being
> 
>  # vector mode r0-r126 increments of 2 (something like that)
>  # scalar mode r0-r63

I added comments to that effect to power_svp64_extra.py and to svp64.mdwn

I rebased on master and pushed to both master and fix-scalar-extra2:

https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=be96bff2a401920cac82dedbc1f7a1c27345e25d

https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=dea437afb25dbf082532a39f8e2d122d079e6b10

> 
> ok i am happy with this, feel free to rebase.
> and let's transfer over the budget from bug #1083

looks like you already did that, thx!

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