[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
an additional unit test suite is needed which puts register values in
to high numbers then say "adds one" to each (sv.addi r80, r80,1) with
say VL=4, and checks that they all are correctly updated.

a set of instructions will have to be selected which cover all 5
categories: NORMAL CROPS BRANCH LDST_IMM LDST_IDX

this will need to be ISACaller/HDL unit tests rather than asm/disasm
tests of binutils.

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