[Libre-soc-isa] [Bug 1161] New: PowerDecoder2 and insndb disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

            Bug ID: 1161
           Summary: PowerDecoder2 and insndb disagree on scalar EXTRA2
                    register encoding for >=r32
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: critical
          Priority: ---
         Component: Specification
          Assignee: programmerjake at gmail.com
          Reporter: programmerjake at gmail.com
                CC: ghostmansd at gmail.com,
                    libre-soc-isa at lists.libre-soc.org, lkcl at lkcl.net,
                    programmerjake at gmail.com
            Blocks: 1044
   NLnet milestone: ---

The originally intended encoding is the tables:
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/svp64.mdwn;h=c623c123a6b544bf01c863d822d36e0bd1c3fc63;hb=9e64850d9de905e3d785b9e2d8a5cec60c0ec439#l1241

note in particular that scalar EXTRA2 is supposed to be able to address every
register from r0 to r63 (vector is every even register from r0 to r126)

The algorithm in the wiki:
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/svp64.mdwn;h=c623c123a6b544bf01c863d822d36e0bd1c3fc63;hb=9e64850d9de905e3d785b9e2d8a5cec60c0ec439#l1195
is incorrect afaict, because it addresses registers r0-31 and r64-95, instead
of r0-63.

PowerDecoder2 and/or insndb need to be fixed since it's based on the algorithm
rather than the tables (TBD which).

I discovered this by running:
sv.maddedu *4, *32, 36, 8
and was confused by why it kept reading RB from register 68 not 36

insndb generates the encoding:
printf "\x00\x29\x40\x05\x32\x22\x28\x10" | pysvp64dis


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=1044
[Bug 1044] SVP64 implementation of pow(x,y,z)
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