[Libre-soc-isa] [Bug 697] SVP64 Reduce Modes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=697

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
def reduce_yield(vl, vec, pred):
    step = 1;
    while step < vl
        redirects = list(range(vl)
        step *= 2;
        for i in (0..vl).step_by(step)
            other = i + step / 2;
            ri = redirects[i]
            ro = redirects[other]
            other_pred = other < vl && pred[ro];
            if pred[ri] && other_pred
                yield (ri, ro)
            else if other_pred
                redirects[ri] = redirects[ro]
            pred[ri] |= other_pred;

i think you'll find that the above eliminates the need for the MV.

it works by having an array of indices which initially start off 0..VL
and whenever you would like to *have had* a mv, instead of performing
an actual mv, the data is left *in place* but the "redirect" array adjusted
dynamically such that a subsequent ADD will take the data from the
in-place location

there are probably some issues to work through (what if no ADD operations
actually take place, what circumstances cause that, and is it really a
problem)

required state for reentrancy: the predicate and the redirects array.

the predicate can be re-read, no problem, as long as Rc=1 hasn't damaged it.

the redirects array can be either cached or it can be restored (slowly)
by re-running up to SVSTATE.srcstep-1 iterations WITHOUT doing any ADDs
at which point redirects should be back to where it should be.

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