[Libre-soc-isa] [Bug 610] New: renumber FP regs as pairs for ELFv2 ABI compliance

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Mar 4 22:40:55 GMT 2021


            Bug ID: 610
           Summary: renumber FP regs as pairs for ELFv2 ABI compliance
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Other
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: oliva at libre-soc.org
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

Since the ELFv2 ABI requires 128-bit VSX registers, and we don't want to
implement VSX, I thought we could group our own 64-bit registers in pairs, each
equivalent to a single VSX register, so that we could comply with the calling
conventions without software emulation of VSX opcodes and registers.

We could accomplish this by shifting our FP register numbers by one bit, so
that only the even-numbered ones would be directly accessible/nameable. 
Getting to the odd-numbered ones would require vectors, which is not unlike
other recent changes that made only registers multiple of certain powers of two
directly nameable.

We'd go from 128 separate 64-bit FP registers to 64 pairs of 64-bit FP
registers, which could pave the way for future extensions that would use the
pairs as a single float128 register.

This amounts to a very tiny actual change to the implementation, that is mainly
a different way of looking at our FP regs so as to avoid a huge performance
penalty we'd incur in ELFv2 VSX emulation.

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