[Libre-soc-isa] [Bug 569] svp64 register predicates vs BE arrays of bits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=569

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_regspec_map.py;h=05ff4814e2504e3acbc5924b614031b460f8bd7c;hb=HEAD#l64

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/cr/main_stage.py;h=43296aefa43c6fc1f6395e8789bc206bf59bc7d9;hb=HEAD#l85

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;h=32cd73321f8c07d59578229a97be261a33b2da2a;hb=HEAD#l497

ah-ha, ah-ha, ah-hahaha *manic insane laughter*

numbering-reversal on CRs but not the target integer register it goes into

ah-hahahahahasob

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