[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Jan 6 19:48:24 GMT 2021


--- Comment #99 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #96)
> i.e. to get the *64* bit scalars to be copied into vectors in the correct
> order is simply not possible and would require a "tag".

64-bit values in registers are byteswapped into the cpu's current endian
*regardless* of if they are accessed as scalars or vector elements.
byte-swapping is *not* limited to SV.

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