[Libre-soc-isa] [Bug 567] Allow transparent scalar loads and stores to/from registers allocated as vectors

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jan 5 18:56:20 GMT 2021


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #0)
> First, note that I'm preemptively marking this as deferred, as I understand
> that we have a kind of feature-freeze right now.

yes.  only spec clarification, not changes to the spec (not at this fundamental

> We can choose arbitrarily, as long as we are consistent. One choice is:
> 8-bit:
> L[0] -> bits 0 to 7
> L[1] -> bits 8 to 15

this is, to my understanding, how NEON encodes elements within registers.  it's
the "LE-byte-numbering, LE-element-numbering" scheme, and it's realistically
the only sane way to do things.

> Another choice is:
> 8-bit:
> L[0] -> bits 56 to 63
> L[1] -> bits 48 to 55

this one is what i termed "MSByte0" after the way that IBM does MSB0 numbering.
 it's extremely hard to understand, conceptualise and think about, and we
should not do it.

MSB0 caused enough problems, requiring weeks of clarification requests to Paul
Mackerras and others on the openpower-hdl-cores list, and resulted in months of
confusion and bug-fixing of the order of months.

to select MSByte0 ordering of the regfile would literally destroy the entire
project's viability.

so, we go with NEON-like encoding.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list