[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #80 from Alexandre Oliva <oliva at libre-soc.org> ---
> can you read VHDL?

I had never tried before this interaction.   I've had no trouble whatsoever
figuring it out.  It's very readable.  I can probably even write it sensibly,
given a body of code to refer to to pick up the constructs from.

What I couldn't find, unsurprisingly, was specification of endianness of
integers.

I couldn't find definitions for directions such as left and right, up and down,
forward and backward either, or colors, either.  Just as expected.

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