[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #68 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #62)

> Note that the HW implementation I proposed in comment #55 would require a
> 5-input mux on ALU pipelines inputs/outputs and a 2-input mux on register
> R/W ports.

no, this is plain wrong, and is misleading alexandre who is not familiar with
gate level design and assessment.

you neglected to mention that those muxes are 64 bits wide.  consequently he
believes that the gate count is only 5.

alexandre: 2 way muxes for one single bit are around 5 gates.  however a mux is
not required here, a crossbar is.  a 2-2 crossbar is 10 gates (basically 2
muxes).  that's per pair of bits.  look up "butterfly network"

also, it's nowhere near as simple as you believe it to be.  plus, muxes are
inadequate.

we are doing 64 bit SIMD backend ALUs.  if the data in the regfile is not
converted to a sane format, then the conversion of every element must be
carried out at the regfile port.

we are designing Dynamic Partitioned SIMD and consequently the 64 bit SIMD must
now  have all possible permutations of byteswapping at the regfile port.

to cover all possibilities we must first enumerate those possibilities.  they
are:

* 8 8 8 8 8 8 8 8
* 16 8 8 8 8 8
* 8 16 8 8 8
* ....
* 16 16 ... 
* 24 8 8 8 ..
* 8 8 ... 16 8..

finally at long last you get to 1x 64 bit. 
total: 128 combinations

to cover all of these REQUIRES a full 8x8 crossbar.

the most efficient method for this is a butterfly network.

and that takes around the 2,000 gates mark for 64 bit 8x8

please understand and accept that the decision has been made: there is just no
way this is practical.

it's not going in.  i can keep on repeating this as many times as it takes to
be accepted: bear in mind that every time i have to repeat it we are wasting
more and more valuable time.

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