[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #66 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #60)
> Ok, here we go.  According to v3.0B p25, a doubleword 0x2122_2324_2526_2728
> is represented in memory like this:
> 
> endianness: { ([offset] = value,)* };
> 
>       from most to least significant
> BE: { [0] = 0x21, [1] = 0x22, [2] = 0x23, [3] = 0x24, [4] = 0x25, [5] =
> 0x26, [6] = 0x27, [7] = 0x28, };
> 
>       from most to least significant
> LE: { [7] = 0x21, [6] = 0x22, [5] = 0x23, [4] = 0x24, [3] = 0x25, [2] =
> 0x26, [1] = 0x27, [0] = 0x28, };

ok, so that describes memory-to-number, where number is in a well-understood
convention from computer science (a hexadecimal representation).

now.

how would, in a scalar v3.0B OpenPOWER processor, you expect that number be
stored in the regfile, in each of the 4 cases?

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