# [Libre-soc-isa] [Bug 623] Switching off parts of the CPU - power saving

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Apr 12 22:26:43 BST 2021

https://bugs.libre-soc.org/show_bug.cgi?id=623

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
We could track state for powered-off parts using something like RISC-V's XS/FS
bit-fields:
https://github.com/riscv/riscv-isa-manual/blob/1271737463c04cacd98320d820a38f66d1c87dae/src/machine.tex#L871

Status  & FS Meaning & XS Meaning\\
\hline
0 & Off     &  All off \\
1 & Initial &  None dirty or clean, some on\\
2 & Clean   &  None dirty, some clean \\
3 & Dirty   &  Some dirty \\

Off is where using those instructions causes a interrupt to OS. The Initial
state would be where the registers are cleared to 0 or whatever values make
sense. If the state is Initial or Off, then registers can be powered-off and
cleared back to their initial value when powered back on. If the state is Clean
or Dirty, then the registers must stay powered-on, though they could be in a
low-power mode. The computational logic can be powered-off in any case.

When the OS next has an interrupt, it can check if the counter has gone past
some additional limit (since just turning off the logic but leaving the
registers powered is a much faster power state to enter/exit, avoiding needing
to involve the OS), then switch the state from Clean or Dirty to Off after
saving the register states. This will allow the HW to turn off the registers
too.

We'd want the XS/FS state anyway to speed up context switches, even if we don't
use it for power-saving.

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