[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 22 03:52:27 BST 2020


--- Comment #86 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
just a reminder jacob of what we have to track, register-wise:

* 8 "fast" SPRs (CTR, LR, TAR, SRR0/1)
* MSR is also in the "fast" list although
  i believe it may need its own DM bits
* 3x XER bits, currently 2 wide, SO CA OV
* 32 INTs (will be 128)
* 32 FP (will be 128)
* 8x CRs (proposed 128) as 4 bit

(all other SPRs i am recommending a "stall and flush")

even as a scalar processor that is a MASSIVE amount.  around 75 wide FU-REGs!

no we cannot not have the CRs (in scalar mode) as "unmanaged" because this is
how you get catastrophic register corruption.  we cannot ignore them either
(scalar non-LibreSOC mode has to be fully OpenPOWER compliant)

therefore we simply have to have CR Dependency Tracking, for all 8 CRs.

in addition to that, the sheer number of regs means that we also need "register
caches" to get the DM size down to "sane" levels.

if we have to do _that_ then including CRs and extending those to 128 is
neither difficult nor problematic once the code is written for INT and FP.

whilst it may then on the face of it seem a  perfectly reasonable next
evolution to add bitlevel DM tracking of an int that is specially treated as a
mask, in a "register cache" context this actually means *bit level PRF ARF

this does not seem to be sane :)

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