[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #84 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #82)
> (In reply to Jacob Lifshay from comment #51)
> 
> > 5. It's ok to deviate from how Power's scalar ISA does things when there's a
> > better way.

to make it clear: because of the potential for rejection by OPF and by other
implementors (hardware and software) if the deviation is too great, i disagree
that deviation should be done "purely because it's better".

by contrast (XER.SO) it is very easy to make a case for improving things (when
parallelised) where PowerISA is, due to the pace of innovation in silicon,
completely broken.  XER.SO was great in 1995 but the READ-MODIFY-WRITE hazards
it created, which were no serious performance bottleneck back then, make even
scalar high-performance PowerISA in 2020 utterly borked, let alone if it's
vectorised.

> just to come back to this, i wrote up the fundamental design principles at
> the top here:
> https://libre-soc.org/openpower/sv/

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