[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Oct 19 22:23:28 BST 2020


--- Comment #71 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #68)

> > the question is, really: realistically what the heck are we doing VL at 64 for,
> > that would use up that many CRs?
> strncat?

oh yeah :)  although a case could be made - my point is, i think, that learning
from POWER10's *eight*-way multi-issue and applying it on on "elwidth=8 VL=16",
would achieve the same end result but without overtaxing the regfiles.

> if we decide to used vectorized CRs we would also need instructions for
> creating dense bitvectors from CRs for all the bitmanip goodness. Similar
> instructions would be needed for 8-bit per lane masks. using 1-bit per lane
> masks bypasses all that since it's already the correct type of bitvector.

i think i kinda worked out (and showed) that this is only true - only practical
- if the 1 bit gets its own DM row.  and if you're going to do that, CRs
already fit that bill.

we _could_ conceivably do bit-level DM subdivision onto 64 bit integer regs
but... no, please, no :)  it makes a mess of the "Register Cache" idea,

whereas CRs we have the freedom *to* decide how many we want to extend it to.

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