[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Oct 19 19:45:09 BST 2020


--- Comment #68 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #67)
> (In reply to Jacob Lifshay from comment #66)
> > the problem is that all 4 bits in each CR field is written by a compare (the
> > most common mask generating operation), effectively changing it to be only
> > useful for 1 mask lane per CR field, since all other masks that could be
> > stored in the CRs are overwritten.
> tck, tck, *thinks*...
> if the limit's 64 CRs (no reason why we should not have 128, and a case
> could be made that, well, 128 int/fp regs therefore 128 CRs) they can be
> copied to intregs (mfcr) and back (mtcr), and in many cases (applying
> esoteric bitmanip ops) that's what would be needed anyway.
> the question is, really: realistically what the heck are we doing VL at 64 for,
> that would use up that many CRs?


if we decide to used vectorized CRs we would also need instructions for
creating dense bitvectors from CRs for all the bitmanip goodness. Similar
instructions would be needed for 8-bit per lane masks. using 1-bit per lane
masks bypasses all that since it's already the correct type of bitvector.

> give me a mo to go over the vector 8-bit mask idea

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