[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Oct 19 13:34:41 BST 2020


--- Comment #62 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

woow, that was dec 2018 :)

the aliasing (the cascade) is the diagram at the top.  after drawing
this out i realised that it would be horrendous to have a combination
of 64-bit FUs, 32-bit FUs, 16-bit FUs *and* 8-bit FUs.

this was where the idea for splitting into 2x 32-bit FUs that "cooperated"
to do 1x 64 bit op came from.

by splitting into 32-bit FUs and then having a small quantity of only 4x 8-bit
FUs we do not end up with the horrendous proliferation in size of the FU-REGS
Dep Matrix, dwarfing the size of the ALUs that they manage.

it would be perfectly fine to add *only* the kinds of operations needed to do
predicate masks broken down to this level of granularity.  LOGICAL pipeline
done @ 8-bit granularity, but not the ADD or MUL pipelines.

of course if someone goes "oh look there's this great 8-bit-level Vector
LOGICAL processing capability, let's hex that until the silicon glows.. oh and
let's do it as predicated ops" then of course there would be contention in the
8-bit RSes.

*but* - hilariously - if they really really wanted to do that then we could
conceivably detect that case and use the *64* bit scalar ops for calculating
the predicate masks!

urr.... my brain has melted.

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