[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=213

--- Comment #55 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #53)
> (In reply to Luke Kenneth Casson Leighton from comment #52)
> > ahh actually, a single scalar intreg as a predicate mask is dead simple. 
> > it's one read.  that's it.
> 
> That's true ... if you completely ignore the need to generate masks.

briefly (it's late here), so i'll just do this one and the rest tomorrow.
i'm not [ignoring it]: i'm assuming that integer scalar
operations (and, xor etc) on those integer scalar registers would
be sufficient to cover the role of generating the masks because the
masks *are* the (one) scalar int reg, the one scalar int reg *is* the
mask.

i.e. once computed (generated) using integer scalar operations that
int reg (mask) goes straight (ok after DM hazard clearance) into the
bit-level subdivision needed to turn it into a vector mask.

what am i missing?  did you mean something different by "need to generate
mask"?
i interpret "generate mask" to be "operations such as bitwise ANDing" and
for that, clearly, straight scalar 64-bit AND is perfectly sufficient.

-- 
You are receiving this mail because:
You are on the CC list for the bug.